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<div class="header">
  <div class="summary">
<a href="#enum-members">Enumerations</a>  </div>
  <div class="headertitle">
<div class="title">Control Register Enums<div class="ingroups"><a class="el" href="group__group__sar.html">SAR          (SAR ADC Subsystem)</a> &raquo; <a class="el" href="group__group__sar__enums.html">Enumerated Types</a></div></div>  </div>
</div><!--header-->
<div class="contents">
<a name="details" id="details"></a><h2 class="groupheader">General Description</h2>
<p>This set of enumerations aids in configuring the SAR CTRL register. </p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="enum-members"></a>
Enumerations</h2></td></tr>
<tr class="memitem:ga35b1b11fbe44b764ba6b6346116e177f"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sar__ctrl__register__enums.html#ga35b1b11fbe44b764ba6b6346116e177f">cy_en_sar_ctrl_pwr_ctrl_vref_t</a> { <br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga35b1b11fbe44b764ba6b6346116e177fade0d2c031e53b1797fbc757abe021db4">CY_SAR_VREF_PWR_100</a> = 0UL &lt;&lt; SAR_CTRL_PWR_CTRL_VREF_Pos, 
<br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga35b1b11fbe44b764ba6b6346116e177fa398a660d1a98069b474713c4a26e383a">CY_SAR_VREF_PWR_80</a> = 1UL &lt;&lt; SAR_CTRL_PWR_CTRL_VREF_Pos, 
<br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga35b1b11fbe44b764ba6b6346116e177fa9a311c392dd64ebc60b5ec18c6207ecc">CY_SAR_VREF_PWR_60</a> = 2UL &lt;&lt; SAR_CTRL_PWR_CTRL_VREF_Pos, 
<br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga35b1b11fbe44b764ba6b6346116e177fa8d0919fee4adb8921b7d0bc686295d1f">CY_SAR_VREF_PWR_50</a> = 3UL &lt;&lt; SAR_CTRL_PWR_CTRL_VREF_Pos, 
<br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga35b1b11fbe44b764ba6b6346116e177fab7a69c39676bd6de5da91c4d19b5cce4">CY_SAR_VREF_PWR_40</a> = 4UL &lt;&lt; SAR_CTRL_PWR_CTRL_VREF_Pos, 
<br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga35b1b11fbe44b764ba6b6346116e177faef42fcf37c15658bc263e86582175118">CY_SAR_VREF_PWR_30</a> = 5UL &lt;&lt; SAR_CTRL_PWR_CTRL_VREF_Pos, 
<br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga35b1b11fbe44b764ba6b6346116e177fa5ef29f130c7268e294ac9b07a767c3b1">CY_SAR_VREF_PWR_20</a> = 6UL &lt;&lt; SAR_CTRL_PWR_CTRL_VREF_Pos, 
<br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga35b1b11fbe44b764ba6b6346116e177fadb90624a19aecabc81c761a951a19501">CY_SAR_VREF_PWR_10</a> = 7UL &lt;&lt; SAR_CTRL_PWR_CTRL_VREF_Pos
<br />
 }<tr class="memdesc:ga35b1b11fbe44b764ba6b6346116e177f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reference voltage buffer power mode definitions.  <a href="group__group__sar__ctrl__register__enums.html#ga35b1b11fbe44b764ba6b6346116e177f">More...</a><br /></td></tr>
</td></tr>
<tr class="separator:ga35b1b11fbe44b764ba6b6346116e177f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8f8244be5b3475b12564d27ce435dc83"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sar__ctrl__register__enums.html#ga8f8244be5b3475b12564d27ce435dc83">cy_en_sar_ctrl_vref_sel_t</a> { <br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga8f8244be5b3475b12564d27ce435dc83a5f2321e40140e516e92a0dd9bd729e2d">CY_SAR_VREF_SEL_BGR</a> = 4UL &lt;&lt; SAR_CTRL_VREF_SEL_Pos, 
<br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga8f8244be5b3475b12564d27ce435dc83adcb52dba59cd63cf2c9fdcfcbe07b007">CY_SAR_VREF_SEL_EXT</a> = 5UL &lt;&lt; SAR_CTRL_VREF_SEL_Pos, 
<br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga8f8244be5b3475b12564d27ce435dc83a46668fff4dd5e85d09a77dac4f5821d3">CY_SAR_VREF_SEL_VDDA_DIV_2</a> = 6UL &lt;&lt; SAR_CTRL_VREF_SEL_Pos, 
<br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga8f8244be5b3475b12564d27ce435dc83a609f8bdeee2cfce3f823f9dfec190900">CY_SAR_VREF_SEL_VDDA</a> = 7UL &lt;&lt; SAR_CTRL_VREF_SEL_Pos
<br />
 }<tr class="memdesc:ga8f8244be5b3475b12564d27ce435dc83"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reference voltage selection definitions.  <a href="group__group__sar__ctrl__register__enums.html#ga8f8244be5b3475b12564d27ce435dc83">More...</a><br /></td></tr>
</td></tr>
<tr class="separator:ga8f8244be5b3475b12564d27ce435dc83"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6c41e98b415fe0fd34cbe3508b5a0903"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sar__ctrl__register__enums.html#ga6c41e98b415fe0fd34cbe3508b5a0903">cy_en_sar_ctrl_bypass_cap_t</a> { <br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga6c41e98b415fe0fd34cbe3508b5a0903aebc0ad5773a22de9f7ad3baa96f12293">CY_SAR_BYPASS_CAP_DISABLE</a> = 0UL &lt;&lt; SAR_CTRL_VREF_BYP_CAP_EN_Pos, 
<br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga6c41e98b415fe0fd34cbe3508b5a0903ad56ab5b6472fac189d368943a2425ed0">CY_SAR_BYPASS_CAP_ENABLE</a> = 1UL &lt;&lt; SAR_CTRL_VREF_BYP_CAP_EN_Pos
<br />
 }<tr class="memdesc:ga6c41e98b415fe0fd34cbe3508b5a0903"><td class="mdescLeft">&#160;</td><td class="mdescRight">Vref bypass cap enable.  <a href="group__group__sar__ctrl__register__enums.html#ga6c41e98b415fe0fd34cbe3508b5a0903">More...</a><br /></td></tr>
</td></tr>
<tr class="separator:ga6c41e98b415fe0fd34cbe3508b5a0903"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga714456a56b0bed98012dc37256b1145c"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sar__ctrl__register__enums.html#ga714456a56b0bed98012dc37256b1145c">cy_en_sar_ctrl_neg_sel_t</a> { <br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga714456a56b0bed98012dc37256b1145ca24b7a5b85507d15f0cb04c55c2dc6436">CY_SAR_NEG_SEL_VSSA_KELVIN</a> = 0UL &lt;&lt; SAR_CTRL_NEG_SEL_Pos, 
<br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga714456a56b0bed98012dc37256b1145ca3c4fb0ec8eb40684d142a370b9bba1ed">CY_SAR_NEG_SEL_P1</a> = 2UL &lt;&lt; SAR_CTRL_NEG_SEL_Pos, 
<br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga714456a56b0bed98012dc37256b1145ca28c775ed6f6eb15215e74b3fe27a2da0">CY_SAR_NEG_SEL_P3</a> = 3UL &lt;&lt; SAR_CTRL_NEG_SEL_Pos, 
<br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga714456a56b0bed98012dc37256b1145caa16a5760a050f5276779e820289186f5">CY_SAR_NEG_SEL_P5</a> = 4UL &lt;&lt; SAR_CTRL_NEG_SEL_Pos, 
<br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga714456a56b0bed98012dc37256b1145ca7a38746f12851aa2069ddda8844c3af7">CY_SAR_NEG_SEL_P7</a> = 5UL &lt;&lt; SAR_CTRL_NEG_SEL_Pos, 
<br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga714456a56b0bed98012dc37256b1145ca7a9aad3ff14fa48199348a1be3460a13">CY_SAR_NEG_SEL_ACORE</a> = 6UL &lt;&lt; SAR_CTRL_NEG_SEL_Pos, 
<br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga714456a56b0bed98012dc37256b1145ca17fcd94823d6172865388780e67e2d9b">CY_SAR_NEG_SEL_VREF</a> = 7UL &lt;&lt; SAR_CTRL_NEG_SEL_Pos
<br />
 }<tr class="memdesc:ga714456a56b0bed98012dc37256b1145c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Negative terminal (Vminus) selection definitions for single-ended channels.  <a href="group__group__sar__ctrl__register__enums.html#ga714456a56b0bed98012dc37256b1145c">More...</a><br /></td></tr>
</td></tr>
<tr class="separator:ga714456a56b0bed98012dc37256b1145c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaed426a773be43a1d02d40fe5bef5349c"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sar__ctrl__register__enums.html#gaed426a773be43a1d02d40fe5bef5349c">cy_en_sar_ctrl_hw_ctrl_negvref_t</a> { <br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#ggaed426a773be43a1d02d40fe5bef5349ca6a71af4d6f3d8c5895247c58003beefd">CY_SAR_CTRL_NEGVREF_FW_ONLY</a> = 0UL &lt;&lt; SAR_CTRL_SAR_HW_CTRL_NEGVREF_Pos, 
<br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#ggaed426a773be43a1d02d40fe5bef5349ca6e6f562eedfea804f48f900b95b99e19">CY_SAR_CTRL_NEGVREF_HW</a> = 1UL &lt;&lt; SAR_CTRL_SAR_HW_CTRL_NEGVREF_Pos
<br />
 }<tr class="memdesc:gaed426a773be43a1d02d40fe5bef5349c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable hardware control of the switch between Vref and the Vminus input.  <a href="group__group__sar__ctrl__register__enums.html#gaed426a773be43a1d02d40fe5bef5349c">More...</a><br /></td></tr>
</td></tr>
<tr class="separator:gaed426a773be43a1d02d40fe5bef5349c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0f2ec6b75df20cba7016f35ef164c181"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sar__ctrl__register__enums.html#ga0f2ec6b75df20cba7016f35ef164c181">cy_en_sar_ctrl_comp_delay_t</a> { <br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga0f2ec6b75df20cba7016f35ef164c181ad149b365524975b9de7f601c1453b444">CY_SAR_CTRL_COMP_DLY_2P5</a> = 0UL &lt;&lt; SAR_CTRL_COMP_DLY_Pos, 
<br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga0f2ec6b75df20cba7016f35ef164c181ac08aabced2b8681e52655c13b9670537">CY_SAR_CTRL_COMP_DLY_4</a> = 1UL &lt;&lt; SAR_CTRL_COMP_DLY_Pos, 
<br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga0f2ec6b75df20cba7016f35ef164c181a761d40317aba2b978450ca924fc59604">CY_SAR_CTRL_COMP_DLY_10</a> = 2UL &lt;&lt; SAR_CTRL_COMP_DLY_Pos, 
<br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga0f2ec6b75df20cba7016f35ef164c181a41a28e14f99014374cc65a747d937a00">CY_SAR_CTRL_COMP_DLY_12</a> = 3UL &lt;&lt; SAR_CTRL_COMP_DLY_Pos
<br />
 }<tr class="memdesc:ga0f2ec6b75df20cba7016f35ef164c181"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configure the comparator latch delay.  <a href="group__group__sar__ctrl__register__enums.html#ga0f2ec6b75df20cba7016f35ef164c181">More...</a><br /></td></tr>
</td></tr>
<tr class="separator:ga0f2ec6b75df20cba7016f35ef164c181"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3b5fb1f5e7ab25bb3fb93ced1eb84c08"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sar__ctrl__register__enums.html#ga3b5fb1f5e7ab25bb3fb93ced1eb84c08">cy_en_sar_ctrl_comp_pwr_t</a> { <br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga3b5fb1f5e7ab25bb3fb93ced1eb84c08a22e30a05a32e743fd283181b9f15cdca">CY_SAR_COMP_PWR_100</a> = 0UL &lt;&lt; SAR_CTRL_COMP_PWR_Pos, 
<br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga3b5fb1f5e7ab25bb3fb93ced1eb84c08a978907998e2818fde6c3073f8715a611">CY_SAR_COMP_PWR_80</a> = 1UL &lt;&lt; SAR_CTRL_COMP_PWR_Pos, 
<br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga3b5fb1f5e7ab25bb3fb93ced1eb84c08a47d61a602711ebfc4599ead19d33e2f2">CY_SAR_COMP_PWR_60</a> = 2UL &lt;&lt; SAR_CTRL_COMP_PWR_Pos, 
<br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga3b5fb1f5e7ab25bb3fb93ced1eb84c08a87a0d9447babc1e29fcb69bfa1e9ddea">CY_SAR_COMP_PWR_50</a> = 3UL &lt;&lt; SAR_CTRL_COMP_PWR_Pos, 
<br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga3b5fb1f5e7ab25bb3fb93ced1eb84c08ada4039f440f5d808d804979de9234dc0">CY_SAR_COMP_PWR_40</a> = 4UL &lt;&lt; SAR_CTRL_COMP_PWR_Pos, 
<br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga3b5fb1f5e7ab25bb3fb93ced1eb84c08a7460044d1bdc08d2fc472455dc4d94c4">CY_SAR_COMP_PWR_30</a> = 5UL &lt;&lt; SAR_CTRL_COMP_PWR_Pos, 
<br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga3b5fb1f5e7ab25bb3fb93ced1eb84c08ae32926b8abc169eaa645e8b5b4cd885d">CY_SAR_COMP_PWR_20</a> = 6UL &lt;&lt; SAR_CTRL_COMP_PWR_Pos, 
<br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga3b5fb1f5e7ab25bb3fb93ced1eb84c08aa091eb38549a69f4a213a1facc0afcf4">CY_SAR_COMP_PWR_10</a> = 7UL &lt;&lt; SAR_CTRL_COMP_PWR_Pos
<br />
 }<tr class="memdesc:ga3b5fb1f5e7ab25bb3fb93ced1eb84c08"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configure the comparator power mode.  <a href="group__group__sar__ctrl__register__enums.html#ga3b5fb1f5e7ab25bb3fb93ced1eb84c08">More...</a><br /></td></tr>
</td></tr>
<tr class="separator:ga3b5fb1f5e7ab25bb3fb93ced1eb84c08"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga73b02bd3911df06c999614e5fb3cc30d"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sar__ctrl__register__enums.html#ga73b02bd3911df06c999614e5fb3cc30d">cy_en_sar_ctrl_sarmux_deep_sleep_t</a> { <br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga73b02bd3911df06c999614e5fb3cc30da03f7cc9c7bf47630541c052e8eaf5616">CY_SAR_DEEPSLEEP_SARMUX_OFF</a> = 0UL &lt;&lt; SAR_CTRL_DEEPSLEEP_ON_Pos, 
<br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga73b02bd3911df06c999614e5fb3cc30da058743f7cee8a55a7ebfca6a6530cd5c">CY_SAR_DEEPSLEEP_SARMUX_ON</a> = 1UL &lt;&lt; SAR_CTRL_DEEPSLEEP_ON_Pos
<br />
 }<tr class="memdesc:ga73b02bd3911df06c999614e5fb3cc30d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable or disable the SARMUX during Deep Sleep power mode.  <a href="group__group__sar__ctrl__register__enums.html#ga73b02bd3911df06c999614e5fb3cc30d">More...</a><br /></td></tr>
</td></tr>
<tr class="separator:ga73b02bd3911df06c999614e5fb3cc30d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0f744ea4e07091484f5587e5466a4a57"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sar__ctrl__register__enums.html#ga0f744ea4e07091484f5587e5466a4a57">cy_en_sar_ctrl_sarseq_routing_switches_t</a> { <br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga0f744ea4e07091484f5587e5466a4a57ae0fe1fa48ba84e1a1d0fc9e3d4e0dcd5">CY_SAR_SARSEQ_SWITCH_ENABLE</a> = 0UL &lt;&lt; SAR_CTRL_SWITCH_DISABLE_Pos, 
<br />
&#160;&#160;<a class="el" href="group__group__sar__ctrl__register__enums.html#gga0f744ea4e07091484f5587e5466a4a57a81471e07bac4eb63b5aaca6c99654115">CY_SAR_SARSEQ_SWITCH_DISABLE</a> = 1UL &lt;&lt; SAR_CTRL_SWITCH_DISABLE_Pos
<br />
 }<tr class="memdesc:ga0f744ea4e07091484f5587e5466a4a57"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable or disable the SARSEQ control of routing switches.  <a href="group__group__sar__ctrl__register__enums.html#ga0f744ea4e07091484f5587e5466a4a57">More...</a><br /></td></tr>
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<h2 class="groupheader">Enumeration Type Documentation</h2>
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<h2 class="memtitle"><span class="permalink"><a href="#ga35b1b11fbe44b764ba6b6346116e177f">&#9670;&nbsp;</a></span>cy_en_sar_ctrl_pwr_ctrl_vref_t</h2>

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          <td class="memname">enum <a class="el" href="group__group__sar__ctrl__register__enums.html#ga35b1b11fbe44b764ba6b6346116e177f">cy_en_sar_ctrl_pwr_ctrl_vref_t</a></td>
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<p>Reference voltage buffer power mode definitions. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="gga35b1b11fbe44b764ba6b6346116e177fade0d2c031e53b1797fbc757abe021db4"></a>CY_SAR_VREF_PWR_100&#160;</td><td class="fielddoc"><p>Full power (100%) </p>
</td></tr>
<tr><td class="fieldname"><a id="gga35b1b11fbe44b764ba6b6346116e177fa398a660d1a98069b474713c4a26e383a"></a>CY_SAR_VREF_PWR_80&#160;</td><td class="fielddoc"><p>80% power </p>
</td></tr>
<tr><td class="fieldname"><a id="gga35b1b11fbe44b764ba6b6346116e177fa9a311c392dd64ebc60b5ec18c6207ecc"></a>CY_SAR_VREF_PWR_60&#160;</td><td class="fielddoc"><p>60% power </p>
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<tr><td class="fieldname"><a id="gga35b1b11fbe44b764ba6b6346116e177fa8d0919fee4adb8921b7d0bc686295d1f"></a>CY_SAR_VREF_PWR_50&#160;</td><td class="fielddoc"><p>50% power </p>
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<tr><td class="fieldname"><a id="gga35b1b11fbe44b764ba6b6346116e177fab7a69c39676bd6de5da91c4d19b5cce4"></a>CY_SAR_VREF_PWR_40&#160;</td><td class="fielddoc"><p>40% power </p>
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<tr><td class="fieldname"><a id="gga35b1b11fbe44b764ba6b6346116e177faef42fcf37c15658bc263e86582175118"></a>CY_SAR_VREF_PWR_30&#160;</td><td class="fielddoc"><p>30% power </p>
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<tr><td class="fieldname"><a id="gga35b1b11fbe44b764ba6b6346116e177fa5ef29f130c7268e294ac9b07a767c3b1"></a>CY_SAR_VREF_PWR_20&#160;</td><td class="fielddoc"><p>20% power </p>
</td></tr>
<tr><td class="fieldname"><a id="gga35b1b11fbe44b764ba6b6346116e177fadb90624a19aecabc81c761a951a19501"></a>CY_SAR_VREF_PWR_10&#160;</td><td class="fielddoc"><p>10% power </p>
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<h2 class="memtitle"><span class="permalink"><a href="#ga8f8244be5b3475b12564d27ce435dc83">&#9670;&nbsp;</a></span>cy_en_sar_ctrl_vref_sel_t</h2>

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          <td class="memname">enum <a class="el" href="group__group__sar__ctrl__register__enums.html#ga8f8244be5b3475b12564d27ce435dc83">cy_en_sar_ctrl_vref_sel_t</a></td>
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<p>Reference voltage selection definitions. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="gga8f8244be5b3475b12564d27ce435dc83a5f2321e40140e516e92a0dd9bd729e2d"></a>CY_SAR_VREF_SEL_BGR&#160;</td><td class="fielddoc"><p>System wide bandgap from <a class="el" href="group__group__sysanalog.html">AREF</a> (Vref buffer on) </p>
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<tr><td class="fieldname"><a id="gga8f8244be5b3475b12564d27ce435dc83adcb52dba59cd63cf2c9fdcfcbe07b007"></a>CY_SAR_VREF_SEL_EXT&#160;</td><td class="fielddoc"><p>External Vref direct from a pin. </p>
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<tr><td class="fieldname"><a id="gga8f8244be5b3475b12564d27ce435dc83a46668fff4dd5e85d09a77dac4f5821d3"></a>CY_SAR_VREF_SEL_VDDA_DIV_2&#160;</td><td class="fielddoc"><p>Vdda/2 (Vref buffer on) </p>
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<tr><td class="fieldname"><a id="gga8f8244be5b3475b12564d27ce435dc83a609f8bdeee2cfce3f823f9dfec190900"></a>CY_SAR_VREF_SEL_VDDA&#160;</td><td class="fielddoc"><p>Vdda. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#ga6c41e98b415fe0fd34cbe3508b5a0903">&#9670;&nbsp;</a></span>cy_en_sar_ctrl_bypass_cap_t</h2>

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<p>Vref bypass cap enable. </p>
<p>When enabled, a bypass capacitor should be connected to the dedicated Vref pin of the device. Refer to the device datasheet for the minimum bypass capacitor value to use. </p>
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="gga6c41e98b415fe0fd34cbe3508b5a0903aebc0ad5773a22de9f7ad3baa96f12293"></a>CY_SAR_BYPASS_CAP_DISABLE&#160;</td><td class="fielddoc"><p>Disable Vref bypass cap. </p>
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<tr><td class="fieldname"><a id="gga6c41e98b415fe0fd34cbe3508b5a0903ad56ab5b6472fac189d368943a2425ed0"></a>CY_SAR_BYPASS_CAP_ENABLE&#160;</td><td class="fielddoc"><p>Enable Vref bypass cap. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#ga714456a56b0bed98012dc37256b1145c">&#9670;&nbsp;</a></span>cy_en_sar_ctrl_neg_sel_t</h2>

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<p>Negative terminal (Vminus) selection definitions for single-ended channels. </p>
<p>The Vminus input for single ended channels can be connected to Vref, VSSA, or routed out to an external pin. The options for routing to a pin are through Pin 1, Pin 3, Pin 5, or Pin 7 of the SARMUX dedicated port or an acore wire in AROUTE, if available on the device.</p>
<p><a class="el" href="group__group__sar__ctrl__register__enums.html#gga714456a56b0bed98012dc37256b1145ca24b7a5b85507d15f0cb04c55c2dc6436">CY_SAR_NEG_SEL_VSSA_KELVIN</a> comes straight from a Vssa pad without any shared branches so as to keep quiet and avoid voltage drops. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="gga714456a56b0bed98012dc37256b1145ca24b7a5b85507d15f0cb04c55c2dc6436"></a>CY_SAR_NEG_SEL_VSSA_KELVIN&#160;</td><td class="fielddoc"><p>Connect Vminus to VSSA_KELVIN. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga714456a56b0bed98012dc37256b1145ca3c4fb0ec8eb40684d142a370b9bba1ed"></a>CY_SAR_NEG_SEL_P1&#160;</td><td class="fielddoc"><p>Connect Vminus to Pin 1 of SARMUX dedicated port. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga714456a56b0bed98012dc37256b1145ca28c775ed6f6eb15215e74b3fe27a2da0"></a>CY_SAR_NEG_SEL_P3&#160;</td><td class="fielddoc"><p>Connect Vminus to Pin 3 of SARMUX dedicated port. </p>
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<tr><td class="fieldname"><a id="gga714456a56b0bed98012dc37256b1145caa16a5760a050f5276779e820289186f5"></a>CY_SAR_NEG_SEL_P5&#160;</td><td class="fielddoc"><p>Connect Vminus to Pin 5 of SARMUX dedicated port. </p>
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<tr><td class="fieldname"><a id="gga714456a56b0bed98012dc37256b1145ca7a38746f12851aa2069ddda8844c3af7"></a>CY_SAR_NEG_SEL_P7&#160;</td><td class="fielddoc"><p>Connect Vminus to Pin 6 of SARMUX dedicated port. </p>
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<tr><td class="fieldname"><a id="gga714456a56b0bed98012dc37256b1145ca7a9aad3ff14fa48199348a1be3460a13"></a>CY_SAR_NEG_SEL_ACORE&#160;</td><td class="fielddoc"><p>Connect Vminus to an ACORE in AROUTE. </p>
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<tr><td class="fieldname"><a id="gga714456a56b0bed98012dc37256b1145ca17fcd94823d6172865388780e67e2d9b"></a>CY_SAR_NEG_SEL_VREF&#160;</td><td class="fielddoc"><p>Connect Vminus to VREF input of SARADC. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#gaed426a773be43a1d02d40fe5bef5349c">&#9670;&nbsp;</a></span>cy_en_sar_ctrl_hw_ctrl_negvref_t</h2>

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<p>Enable hardware control of the switch between Vref and the Vminus input. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="ggaed426a773be43a1d02d40fe5bef5349ca6a71af4d6f3d8c5895247c58003beefd"></a>CY_SAR_CTRL_NEGVREF_FW_ONLY&#160;</td><td class="fielddoc"><p>Only firmware control of the switch. </p>
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<tr><td class="fieldname"><a id="ggaed426a773be43a1d02d40fe5bef5349ca6e6f562eedfea804f48f900b95b99e19"></a>CY_SAR_CTRL_NEGVREF_HW&#160;</td><td class="fielddoc"><p>Enable hardware control of the switch. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#ga0f2ec6b75df20cba7016f35ef164c181">&#9670;&nbsp;</a></span>cy_en_sar_ctrl_comp_delay_t</h2>

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<p>Configure the comparator latch delay. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="gga0f2ec6b75df20cba7016f35ef164c181ad149b365524975b9de7f601c1453b444"></a>CY_SAR_CTRL_COMP_DLY_2P5&#160;</td><td class="fielddoc"><p>2.5 ns delay, use for SAR conversion rate up to 2.5 Msps </p>
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<tr><td class="fieldname"><a id="gga0f2ec6b75df20cba7016f35ef164c181ac08aabced2b8681e52655c13b9670537"></a>CY_SAR_CTRL_COMP_DLY_4&#160;</td><td class="fielddoc"><p>4 ns delay, use for SAR conversion rate up to 2.0 Msps </p>
</td></tr>
<tr><td class="fieldname"><a id="gga0f2ec6b75df20cba7016f35ef164c181a761d40317aba2b978450ca924fc59604"></a>CY_SAR_CTRL_COMP_DLY_10&#160;</td><td class="fielddoc"><p>10 ns delay, use for SAR conversion rate up to 1.5 Msps </p>
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<tr><td class="fieldname"><a id="gga0f2ec6b75df20cba7016f35ef164c181a41a28e14f99014374cc65a747d937a00"></a>CY_SAR_CTRL_COMP_DLY_12&#160;</td><td class="fielddoc"><p>12 ns delay, use for SAR conversion rate up to 1 Msps </p>
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<h2 class="memtitle"><span class="permalink"><a href="#ga3b5fb1f5e7ab25bb3fb93ced1eb84c08">&#9670;&nbsp;</a></span>cy_en_sar_ctrl_comp_pwr_t</h2>

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<p>Configure the comparator power mode. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="gga3b5fb1f5e7ab25bb3fb93ced1eb84c08a22e30a05a32e743fd283181b9f15cdca"></a>CY_SAR_COMP_PWR_100&#160;</td><td class="fielddoc"><p>100% power, use this for &gt; 2 Msps </p>
</td></tr>
<tr><td class="fieldname"><a id="gga3b5fb1f5e7ab25bb3fb93ced1eb84c08a978907998e2818fde6c3073f8715a611"></a>CY_SAR_COMP_PWR_80&#160;</td><td class="fielddoc"><p>80% power, use this for 1.5 - 2 Msps </p>
</td></tr>
<tr><td class="fieldname"><a id="gga3b5fb1f5e7ab25bb3fb93ced1eb84c08a47d61a602711ebfc4599ead19d33e2f2"></a>CY_SAR_COMP_PWR_60&#160;</td><td class="fielddoc"><p>60% power, use this for 1.0 - 1.5 Msps </p>
</td></tr>
<tr><td class="fieldname"><a id="gga3b5fb1f5e7ab25bb3fb93ced1eb84c08a87a0d9447babc1e29fcb69bfa1e9ddea"></a>CY_SAR_COMP_PWR_50&#160;</td><td class="fielddoc"><p>50% power, use this for 500 ksps - 1 Msps </p>
</td></tr>
<tr><td class="fieldname"><a id="gga3b5fb1f5e7ab25bb3fb93ced1eb84c08ada4039f440f5d808d804979de9234dc0"></a>CY_SAR_COMP_PWR_40&#160;</td><td class="fielddoc"><p>40% power, use this for 250 - 500 ksps </p>
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<tr><td class="fieldname"><a id="gga3b5fb1f5e7ab25bb3fb93ced1eb84c08a7460044d1bdc08d2fc472455dc4d94c4"></a>CY_SAR_COMP_PWR_30&#160;</td><td class="fielddoc"><p>30% power, use this for 100 - 250 ksps </p>
</td></tr>
<tr><td class="fieldname"><a id="gga3b5fb1f5e7ab25bb3fb93ced1eb84c08ae32926b8abc169eaa645e8b5b4cd885d"></a>CY_SAR_COMP_PWR_20&#160;</td><td class="fielddoc"><p>20% power, use this for TDB sps </p>
</td></tr>
<tr><td class="fieldname"><a id="gga3b5fb1f5e7ab25bb3fb93ced1eb84c08aa091eb38549a69f4a213a1facc0afcf4"></a>CY_SAR_COMP_PWR_10&#160;</td><td class="fielddoc"><p>10% power, use this for &lt; 100 ksps </p>
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<h2 class="memtitle"><span class="permalink"><a href="#ga73b02bd3911df06c999614e5fb3cc30d">&#9670;&nbsp;</a></span>cy_en_sar_ctrl_sarmux_deep_sleep_t</h2>

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<p>Enable or disable the SARMUX during Deep Sleep power mode. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="gga73b02bd3911df06c999614e5fb3cc30da03f7cc9c7bf47630541c052e8eaf5616"></a>CY_SAR_DEEPSLEEP_SARMUX_OFF&#160;</td><td class="fielddoc"><p>Disable SARMUX operation during Deep Sleep. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga73b02bd3911df06c999614e5fb3cc30da058743f7cee8a55a7ebfca6a6530cd5c"></a>CY_SAR_DEEPSLEEP_SARMUX_ON&#160;</td><td class="fielddoc"><p>Enable SARMUX operation during Deep Sleep. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#ga0f744ea4e07091484f5587e5466a4a57">&#9670;&nbsp;</a></span>cy_en_sar_ctrl_sarseq_routing_switches_t</h2>

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          <td class="memname">enum <a class="el" href="group__group__sar__ctrl__register__enums.html#ga0f744ea4e07091484f5587e5466a4a57">cy_en_sar_ctrl_sarseq_routing_switches_t</a></td>
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<p>Enable or disable the SARSEQ control of routing switches. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="gga0f744ea4e07091484f5587e5466a4a57ae0fe1fa48ba84e1a1d0fc9e3d4e0dcd5"></a>CY_SAR_SARSEQ_SWITCH_ENABLE&#160;</td><td class="fielddoc"><p>Enable the SARSEQ to change the routing switches defined in the channel configurations. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga0f744ea4e07091484f5587e5466a4a57a81471e07bac4eb63b5aaca6c99654115"></a>CY_SAR_SARSEQ_SWITCH_DISABLE&#160;</td><td class="fielddoc"><p>Disable the SARSEQ. </p>
<p>It is up to the firmware to set the routing switches </p>
</td></tr>
</table>

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